HT48R02 datasheet(8/38 Pages) HOLTEK

8 / 38 page

HT48R01/HT48R02/HT48R03

Rev. 1.00

December 20, 2006

word are transferred to the lower portion of TBLH, and

the remaining 2 bits are read as

²0². The Table

Higher-order byte register (TBLH) is read only. The ta-

ble pointer (TBLP) is a read/write register (07H),

which indicates the table location. Before accessing

the table, the location must be placed in TBLP. The

TBLH is read only and cannot be restored. If the main

routine and the ISR (Interrupt Service Routine) both

employ the table read instruction, the contents of the

TBLH in the main routine are likely to be changed by

the table read instruction used in the ISR, and errors

may occur. Therefore, using the table read instruction

in the main routine and the ISR simultaneously should

be avoided. However, if the table read instruction has

to be applied in both the main routine and the ISR, the

interrupt is supposed to be disabled prior to the table

read instruction. It will not be enabled until the TBLH

has been backed up. All table related instructions re-

quire two cycles to complete the operation. These ar-

eas may function as normal program memory

depending upon the requirements.

Stack Register

- STACK

This is a special part of the memory which is used to save

the contents of the Program Counter only. The stack is or-

ganised up to 8 levels and is neither part of the data nor

part of the program space, and is neither readable nor

writable. The activated level is indexed by the stack

pointer (SP) and is neither readable nor writeable. At a

subroutine call or interrupt acknowledgment, the con-

tents of the program counter are pushed onto the stack.

At the end of a subroutine or an interrupt routine, signaled

by a return RET or RETI instruction, the program counter

is restored to its previous value from the stack. After a

chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledgment will be inhibited. When the stack

pointer is decremented by RET or RETI, the interrupt will

be serviced. This feature prevents stack overflow allow-

ing the programmer to use the structure more easily. In a

similar case, if the stack is full and a

²CALL² is subse-

quently executed, a stack overflow occurs and the first

entry will be los. Only the most recent 4 return ad-

dresses are stored.

Data Memory

- RAM

The data memory is divided into two functional groups:

special function registers and general purpose data

memory 64

´8 for the HT48R01, 96´8 for the HT48R02

or 160

´8 for the HT48R03. Most are read/write, but

some are read only.

The unused space before 20H is reserved for future ex-

panded usage and reading these locations will get

²00H². The general purpose data memory, addressed

from 20H to 5FH (HT48R01), 20H to 7FH (HT48R02)

or 20H to BFH (HT48R03), is used for data and control

information under instruction commands.

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by

²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer register (MP;01H).

Indirect Addressing Register

Location 00H/02H are indirect addressing registers that

are not physically implemented. Any read/write opera-

tion of [00H]/[02H] accesses data memory pointed to by

MP0 (01H)/MP1 (03H). Reading location 00H itself indi-

rectly will return the result 00H. Writing indirectly results

in no operation.

The memory pointer registers (MP0/MP1) are 7-bit

registers (HT48R01/HT48R02) or 8 bit registers

(HT48R03). The bit 7 of MP0/MP1 (HT48R01/

HT48R02) are undefined and reading will return the

result

²1². Any writing operation to MP0/MP1 will only

transfer the lower 7-bit data to MP.

Accumulator

The accumulator is closely related to ALU operations. It

is also mapped to location 05H of the data memory and

can carry out immediate data operations. The data

movement between two data memory locations must

pass through the accumulator.

Arithmetic and Logic Unit

- ALU

This circuit performs 8-bit arithmetic and logic opera-

tions. The ALU provides the following functions:

· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

· Logic operations (AND, OR, XOR, CPL)

· Rotation (RL, RR, RLC, RRC)

· Increment and Decrement (INC, DEC)

· Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of data operations

but also changes the status register.

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