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80221 bảng dữ liệu(PDF) 31 Page - LSI Computer Systems |
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80221 bảng dữ liệu(HTML) 31 Page - LSI Computer Systems |
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31 / 91 page ![]() 80220/80221 4-31 MD400159/E 31 INTERNAL INTERRUPT MDC MDIO MDIO HI-Z PULLED HIGH EXTERNALLY MDIO HI-Z PULLED HIGH EXTERNALLY INTERRUPT PULSE INTERNAL INTERRUPT MDC MDIO LAST TWO BITS OF READ CYCLE MDIO HI-Z PULLED HIGH EXTERNALLY INTERRUPT PULSE MDIO HI-Z PULLED HIGH EXTERNALLY B0 B1 Figure 10. MDIO Interrupt Pulse this bit is set, an interrupt is signalled by an low going pulse on MDIO when MDC is high and the serial port is in the idle state, as shown in the timing diagram in Figure 10. Once MDIO is forced low to indicate the interrupt condition, MDIO stays low until MDC returns low. Once MDC returns a.) Interrupt Happens During Idle. b.) Interrupt Happens During Read Cycle. low, then MDIO goes back to high impedance state. If the interrupt occurs while the serial port is being accessed, then the MDIO interrupt pulse is delayed until one clock bit after the serial port access cycle is ended as shown in Figure 10. |
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