6 / 78 page
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
REV 1.1
12/2001
6
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Block Diagram (64Mb x 4)
1
DQS
CK, CK
DLL
RAS
CAS
CK
CS
WE
CK
Column-Address
Counter/Latch
Mode
11
A0-A12,
BA0, BA1
CKE
13
15
I/O Gating
DM Mask Logic
Bank0
Memory
Array
(8192 x 1024 x 8)
Sense Amplifiers
Bank1
Bank2
Bank3
13
10
1
2
2
4
4
4
Input
Register
1
1
1
1
1
8
8
2
8
clk
out
Data
Mask
Data
CK,
COL0
COL0
COL0
clk
in
DQS
Generator
4
4
4
4
4
8
DQ0-DQ3,
DM
DQS
1
Write
FIFO
&
Drivers
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Column
Decoder
1024
(x8)
Registers
8192
15
CK
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
