UPD75P3036 datasheet(39/67 Pages) RENESAS

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µPD75P3036

Data Sheet U11575EJ1V1DS

Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85

°C, VDD = 1.8 to 5.5 V)

Resonator

Recommended

Parameter

Conditions

MIN.

TYP.

MAX.

Unit

Constants

Crystal

Oscillation frequency

32.768

kHz

resonator

(fXT)Note 1

Oscillation

VDD = 4.5 to 5.5 V

1.0

stabilization timeNote 2

External

XT1 input frequency

100

kHz

clock

(fXT)Note 1

XT1 input high-,

µs

low-level widths

(tXTH, tXTL)

Notes 1.

The oscillation frequency shown above indicate characteristics of the oscillation circuit only. For the

instruction execution time, refer to AC Characteristics.

The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been

applied.

Caution When using the subsystem clock oscillation circuit, wire the portion enclosed in the dotted line

in the above figure as follows to prevent adverse influence due to wiring capacitance:

•

Keep the wiring length as short as possible.

•

Do not cross the wiring with other signal lines.

•

Do not route the wiring in the vicinity of a line through which a high alternating current flows.

•

Always keep the ground point of the capacitor of the oscillation circuit at the same potential

as VDD.

•

Do not ground to a power supply pattern through which a high current flows.

•

Do not extract signals from the oscillation circuit.

The subsystem clock oscillation circuit has a low amplification factor to reduce current

dissipation and is more susceptible to noise than the main system clock oscillation circuit.

Therefore, exercise utmost care in wiring the subsystem clock oscillation circuit.

XT1

XT2

VDD

XT1

XT2

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