AD5539

–13–

REV. B

APPLICATIONS SUMMARY CHART

GAIN

3 dB

R1

R2

1

2

2

GAIN

FLATNESS

BANDWIDTH

(TRIMMED)

Gain = –1 to –5

Circuit of Fig. 17

R2

G

2 k

≤

R1

4

R1

R2

–1

≥

1

2

LAG

≈

3pF

G

–2

±0.2 dB

200 MHz

Gain = –1 to –5

Circuit of Fig. 23

R2

G

2 k

≤

R1

4

R1

R2

–1

≥

1

2

LAG

≈

3pF

G

–2

±1 dB

180 MHz

Gain = +2 to +5

3

Circuit of Fig. 27

R2

G –1

2 k

≤

R1

10

R1

R2

–1

≥

1

2

LAG

≈

3 pF

G –1

+3

±1 dB

390 MHz

Gain = +2 to +5

4

Circuit of Fig. 29

R2

G –1

2 k

≤

R1

10

R1

R2

–1

NA

≈

3 pF

G –1

+3

±0.5 dB

340 MHz

Gain < –5

R2

G

1.5 k

NA

NA

Trimmer

5

–20

±0.2 dB

80 MHz

Gain > +5

R2

G –1

1.5 k

NA

NA

Trimmer

5

+20

±0.2 dB

80 MHz

NOTES

G = Gain

NA = Not Applicable

The photos of Figures 40 and 41 demonstrate how the AD5539

easily settles to 1% (1 mV) in less than 12 ns; settling to 0.1%

(100

µV) requires less than 25 ns.

Figure 40. Error Signal from AD5539 Settling Time Test

Circuit – Falling Edge. Vertical Scale: 5 ns/div.; Horizontal

Scale: 500

µV/div

Figure 41. Error Signal from AD5539 Settling Time Test

Circuit – Rising Edge. Vertical Scale: 5 ns/div.; Horizontal

Scale: 500

µV/div