L6714 datasheet(47/70 Pages) STMICROELECTRONICS

47 / 70 page

L6714

Output voltage monitor and protections

47/70

Output voltage monitor and protections

L6714 monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP

and PGOOD (when applicable) conditions. The device shows different thresholds when

programming different operation mode (Intel or AMD, See Table 10) but the behavior in

response to a protection event is still the same as described below.

Protections are active also during soft-start (See “Soft start” Section) while are masked

during D-VID transitions with an additional 32 clock cycle delay after the transition has

finished to avoid false triggering.

16.1

Under voltage

If the output voltage monitored by VSEN drops more than -750mV below the programmed

reference for more than one clock period, L6714 turns off all MOSFET and latches the

condition: to recover it is required to cycle Vcc or the OUTEN pin. This is independent of the

selected operative mode.

16.2

Preliminary over voltage

To provide a protection while VCC is below the UVLOVCC threshold is fundamental to avoid

damage to the CPU in case of failed HS MOSFET. In fact, since the device is supplied from

the 12V bus, it is basically “blind” for any voltage below the turn-on threshold (UVLOVCC). In

order to give full protection to the load, a preliminary-OVP protection is provided while VCC

is within UVLOVCC and UVLOOVP.

This protection turns-on the low side MOSFET as long as the FBR pin voltage is greater

than 1.800V with a 350mV hysteresis. When set, the protection drives the LS MOSFET with

a gate-to-source voltage depending on the voltage applied to VCCDRx and independently

by the turn-ON threshold across these pins (UVLOVCCDR). This protection depends also on

the OUTEN pin status as detailed in Figure 18.

A simple way to provide protection to the output in all conditions when the device is OFF

(then avoiding the unprotected red region in Figure 18-Left) consists in supplying the

controller through the 5VSB bus as shown in Figure 18-Right: 5VSB is always present before

+12V and, in case of HS short, the LS MOSFET is driven with 5V assuring a reliable

protection of the load. Preliminary OVP is always active before UVLOVCC for both Intel and

AMD Modes.

Figure 18. Output voltage protections and typical principle connections

VCC

VCCDR1

VCCDR2

VCCDR3

+12V

+5V

Vcc

UVLO

OVP

UVLO

VCC

Preliminary OVP Enabled

FBR Monitored

No Protection

Provided

(OUTEN = 1)

Programmable OVP

VSEN Monitored

(OUTEN = 0)

Preliminary OVP

FBR Monitored

L6714 bảng dữ liệu(PDF) 47 Page - STMicroelectronics

L6714 bảng dữ liệu(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

bảng dữ liệu tải về

Link URL