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M16C/62 bảng dữ liệu(PDF) 58 Page - Renesas Technology Corp |
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M16C/62 bảng dữ liệu(HTML) 58 Page - Renesas Technology Corp |
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58 / 87 page ![]() VCC1 = VCC2 = 3V M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62P) 4 8 f o 3 0 0 2 , 7 0 . v o N 0 1 . 2 . v e R page 58 Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Figure 5.11 Ports P0 to P14 Measurement Circuit Table 5.46 Memory Expansion, Microprocessor Modes (for setting with no wait) Symbol Standard Measuring condition Max. Min. Parameter Unit td(BCLK-AD) Address output delay time30 ns th(BCLK-AD) Address output hold time (refers to BCLK)4 ns th(BCLK-CS) Chip select output hold time (refers to BCLK)4 ns td(BCLK-ALE) ALE signal output delay time25 ns th(BCLK-ALE) ALE signal output hold time –4 ns td(BCLK-RD) RD signal output delay time30 ns th(BCLK-RD) RD signal output hold time0 ns td(BCLK-WR) WR signal output delay time30 ns th(BCLK-WR) WR signal output hold time0 ns td(BCLK-DB) Data output delay time (refers to BCLK)40 ns th(BCLK-DB) Data output hold time (refers to BCLK)(3) 4ns th(WR-DB) Data output hold time (refers to WR)(3) ns td(DB-WR) Data output delay time (refers to WR)ns 1. Calculated according to the BCLK frequency as follows: f(BCLK) 0.5 X 109 – 40 [ns] td(BCLK-CS) Chip select output delay time30 ns th(RD-AD) Address output hold time (refers to RD)0 ns th(WR-AD) Address output hold time (refers to WR) (Note 2) ns 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1k Ω, hold time of output “L” level is t = – 30pF X 1k Ω X ln (1 – 0.2VCC2 / VCC2) = 6.7ns. DBi R C (Note 1) (Note 2) 2. Calculated according to the BCLK frequency as follows: f(BCLK) 0.5 X 109 [ns] f(BCLK) is 12.5MHz or less. – 10 NOTES: HLDA output delay time 40 ns td(BCLK-HLDA) See Figure 5.11 P6 P7 P8 P10 P9 P0 P1 P2 P3 P4 P5 30pF P11 P12 P13 P14 |
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