Nexperia

74LVC10A

Triple 3-input NAND gate

4. Functional diagram

mna757

3Y

3C

11

3B

10

3A

9

2C

5

2B

4

2A

3

1C

13

1B

2

1A

1

8

2Y

6

1Y

12

Fig. 1. Logic symbol

mna759

12

&

&

&

6

8

13

2

1

5

4

3

11

10

9

Fig. 2. IEC logic symbol

mna758

A

B

C

Y

Fig. 3. Logic diagram (one gate)

5. Pinning information

5.1. Pinning

74LVC10A

1A

VCC

1B

1C

2A

1Y

2B

3C

2C

3B

2Y

3A

GND

3Y

001aad047

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 4. Pin configuration SOT108-1 (SO14) and

SOT402-1 (TSSOP14)

001aad048

74LVC10A

GND(1)

Transparent top view

2Y

3A

2C

3B

2B

3C

2A

1Y

1B

1C

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 5. Pin configuration SOT762-1 (DHVQFN14)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1A, 2A, 3A

1, 3, 9

data input

1B, 2B, 3B

2, 4, 10

data input

1C, 2C, 3C

13, 5, 11

data input

1Y, 2Y, 3Y

12, 6, 8

data output

GND

7

ground (0 V)

VCC

14

supply voltage

74LVC10A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 6 — 15 April 2021

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