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74LVC10AD bảng dữ liệu(PDF) 5 Page - Nexperia B.V. All rights reserved |
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74LVC10AD bảng dữ liệu(HTML) 5 Page - Nexperia B.V. All rights reserved |
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5 / 12 page ![]() Nexperia 74LVC10A Triple 3-input NAND gate 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 7. -40 °C to +85 °C -40 °C to +125 °C Symbol Parameter Conditions Min Typ[1] Max Min Max Unit nA, nB, nC to nY; see Fig. 6 [2] VCC = 1.2 V - 13 - - - ns VCC = 1.65 V to 1.95 V 0.5 4.5 11.2 0.5 12.9 ns VCC = 2.3 V to 2.7 V 1.0 2.7 6.3 1.0 7.4 ns VCC = 2.7 V 1.5 2.8 6.7 1.5 7.8 ns tpd propagation delay VCC = 3.0 V to 3.6 V 1.5 2.4 5.7 1.5 6.6 ns per gate; VI = GND to VCC [3] VCC = 1.65 V to 1.95 V - 2.9 - - - pF VCC = 2.3 V to 2.7 V - 6.0 - - - pF CPD power dissipation capacitance VCC = 3.0 V to 3.6 V - 8.8 - - - pF [1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL x VCC 2 x fo) = sum of the outputs 74LVC10A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 — 15 April 2021 5 / 12 |
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