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NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
REV 1.0
May, 2001
39
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Read Cycle
Symbol
Parameter
-7K
-75B
-8B
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
tOH
Data Out Hold Time
—
—
—
—
2.5
—
ns
1
2.7
—
2.7
—
3
—
ns
2, 4
tLZ
Data Out to Low Impedance Time
0
—
0
—
0
—
ns
tHZ3
Data Out to High Impedance Time
3
5.4
3
5.4
3
6
ns
3
tHZ2
Data Out to High Impedance Time
3
5.4
3
6
3
6
ns
3
tDQZ
DQM Data Out Disable Latency
2
—
2
—
2
—
CK
1. AC Output Load Circuit A.
2. AC Output Load Circuit B.
3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
4. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A).
Refresh Cycle
Symbol
Parameter
-7K
-75B
-8B
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
tREF
Refresh Period
—
64
—
64
—
64
ms
1
tSREX
Self Refresh Exit Time
10
—
10
—
10
—
ns
1. 8192 a uto refresh cycles.
Write Cycle
Symbol
Parameter
-7K
-75B
-8B
Units
Min.
Max.
Min.
Max.
Min.
Max.
tDS
Data In Set-up Time
1.5
—
1.5
—
2
—
ns
tDH
Data In Hold Time
0.8
—
0.8
—
1
—
ns
tDPL
Data input to Precharge
15
—
15
—
20
—
ns
tDAL3
Data In to Active Delay
CAS Latency = 3
5
—
5
—
5
—
CK
tDAL2
Data In to Active Delay
CAS Latency = 2
5
—
5
—
5
—
CK
tDQW
DQM Write Mask Latency
0
—
0
—
0
—
CK
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