MC68340 datasheet(194/441 Pages) FREESCALE

194 / 441 page

MOTOROLA

MC68340 USER’S MANUAL

5- 57

exception is also stacked. This data is placed on the stack in the format shown in Figure

5-13. The return address from the initial exception is stacked for RTE .

5.5.3.2 CORRECTING A FAULT. There are two ways to complete a faulted released write

bus cycle. The first is to use a software handler. The second is to rerun the bus cycle via

RTE.

Type II fault handlers must terminate with RTE, but specific requirements must also be

met before an instruction is restarted.

There are three varieties of type III operand fault recovery. The first is completion of an

instruction in software. The second is conversion to type II with restart via RTE. The third

is continuation from the fault via RTE.

5.5.3.2.1 Type I—Completing Released Writes via Software. To complete a bus cycle

in software, a handler must first read the SSW function code field to determine the

appropriate address space, access the fault address pointer on the stack, and then

transfer data from the stacked image of the output buffer to the fault address.

Because the CPU32 has a 16-bit internal data bus, long operands require two bus

accesses. A fault during the second access of a long operand causes the LG bit in the

SSW to be set. The SIZ field indicates remaining operand size. If operand coherency is

important, the complete operand must be rewritten. After a long operand is rewritten, the

RR bit must be cleared. Failure to clear the RR bit can cause the RTE instruction to rerun

the bus cycle. Following rewrite, it is not necessary to adjust the PC (or other stack

contents) before executing RTE.

5.5.3.2.2 Type I—Completing Released Writes via RTE. An exception handler can use

the RTE instruction to complete a faulted bus cycle. When RTE executes, the fault

address, data output buffer, PC, and SR are restored from the stack. Any pending

breakpoint or trace exceptions, as indicated by TR, B1, and B0 in the stacked SSW, are

requeued during SSW restoration. The RR bit in the SSW is checked during the

unstacking operation; if it is set, the RW, FUNC, and SIZ fields are restored and the

released write cycle is rerun.

To maintain long-word operand coherence, stack contents must be adjusted prior to RTE

execution. The fault address must be decremented by 2 if LG is set and SIZ indicates a

remaining byte or word. SIZ must be set to long. All other fields should be left unchanged.

The bus controller uses the modified fault address and SIZ field to rerun the complete

released write cycle.

Manipulating the stacked SSW can cause unpredictable results because RTE checks only

the RR bit to determine if a bus cycle must be rerun. Inadvertent alteration of the control

bits could cause the bus cycle to be a read instead of a write or could cause access to a

different address space than the original bus cycle. If the rerun bus cycle is a read,

returned data will be ignored.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68340 bảng dữ liệu(PDF) 194 Page - Freescale Semiconductor, Inc

MC68340 bảng dữ liệu(HTML) 194 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL