MC68340 datasheet(190/441 Pages) FREESCALE

190 / 441 page

MOTOROLA

MC68340 USER’S MANUAL

5- 53

The TP field defines the class of the faulted bus operation. Two bus error exception

frame types are defined. One is for faults on prefetch and operand accesses, and the

other is for faults during exception frame stacking:

0 = Operand or prefetch bus fault

1 = Exception processing bus fault

MV is set when the operand transfer portion of the MOVEM instruction is in progress at

the time of a bus fault. If a prefetch bus fault occurs while prefetching the MOVEM

opcode and extension word, both the MV and IN bits will be set.

0 = MOVEM was not in progress when fault occurred

1 = MOVEM was in progress when fault occurred

TR indicates that a trace exception was pending when a bus error exception was

processed. The instruction that generated the trace will not be restarted upon return

from the exception handler. This includes MOVEM and released write bus errors

indicated by the assertion of either MV or RR in the SSW.

0 = Trace not pending

1 = Trace pending

B1 indicates that a breakpoint exception was pending on channel 1 (external breakpoint

source) when a bus error exception was processed. Pending breakpoint status is

stacked, regardless of the type of bus error exception.

0 = Breakpoint not pending

1 = Breakpoint pending

B0 indicates that a breakpoint exception was pending on channel 0 (internal breakpoint

source) when the bus error exception was processed. Pending breakpoint status is

stacked, regardless of the type of bus error exception.

0 = Breakpoint not pending

1 = Breakpoint pending

RR will be set if the faulted bus cycle was a released write. A released write is one that

is overlapped. If the write is completed (rerun) in the exception handler, the RR bit

should be cleared before executing RTE. The bus cycle will be rerun if the RR bit is set

upon return from the exception handler.

0 = Faulted cycle was read, RMW, or unreleased write

1 = Faulted cycle was a released write

Faulted RMW bus cycles set the RM bit. RM is ignored during unstacking.

0 = Faulted cycle was non-RMW cycle

1 = Faulted cycle was either the read or write of an RMW cycle

Instruction prefetch faults are distinguished from operand (both read and write) faults by

the IN bit. If IN is cleared, the error was on an operand cycle; if IN is set, the error was

on an instruction prefetch. IN is ignored during unstacking.

0 = Operand

1 = Prefetch

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