MC68340 datasheet(125/441 Pages) FREESCALE

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MC68340 USER’S MANUAL

MOTOROLA

4.3.2.8 SOFTWARE SERVICE REGISTER (SWSR). The SWSR is the location to which

the software watchdog servicing sequence is written. The software watchdog can be

enabled or disabled by the SWE bit in the SYPCR. SWSR can be written at any time, but

returns all zeros when read.

SWSR

$027

76543210

SWSR7 SWSR6 SWSR5 SWSR4 SWSR3 SWSR2 SWSR1 SWSR0

RESET:

00000000

Supervisor Only

4.3.3 Clock Synthesizer Control Register (SYNCR)

The SYNCR can be read or written only in supervisor mode. The reset state of SYNCR

produces an operating frequency of 8.39 MHz when the PLL is referenced to a 32.768-

kHz reference signal. The system frequency is controlled by the frequency control bits in

the upper byte of the SYNCR as follows:

FSYSTEM = FCRYSTAL [2

(2+2W+X) ]

× (Y+1)

SYNCR

$004

9876543210

RSVD

SLIMP

SLOCK

RSTEN

STSIM

STEXT

RESET:

00111111000U

000

U = Unaffected by reset

Supervisor Only

W—Frequency Control Bit

This bit controls the prescaler tap in the synthesizer feedback loop. Setting the bit

increases the VCO speed by a factor of 4, requiring a time delay for the VCO to relock

(see equation for determining system frequency).

X—Frequency Control Bit

This bit controls a divide-by-two prescaler, which is not in the synthesizer feedback

loop. Setting the bit doubles the system clock speed without changing the VCO speed,

as specified in the equation for determining system frequency; therefore, no delay is

incurred to relock the VCO.

Y5–Y0—Frequency Control Bits

The Y-bits, with a value from 0–63, control the modulus downcounter in the synthesizer

feedback loop, causing it to divide by the value of Y+1 (see the equation for determining

system frequency). Changing these bits requires a time delay for the VCO to relock.

Bits 7–5—Reserved

Bit 7 is reserved for factory testing.

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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