MC68340 datasheet(248/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

5- 111

5.7.3.12 CONTROL INSTRUCTIONS. The control instruction table indicates the number

of clock periods needed for the processor to perform the specified operation on the given

addressing mode. Footnotes indicate when to account for the appropriate EA times. The

total number of clock cycles is outside the parentheses. The numbers inside parentheses

(r/p/w) are included in the total clock cycle number. All timing data assumes two-clock

reads and writes.

Instruction

Head

Tail

Cycles

ANDI

#, SR

−2

12(0/2/0)

EORI

#, SR

−2

12(0/2/0)

ORI

#, SR

−2

12(0/2/0)

ANDI

#, CCR

6(0/2/0)

EORI

#, CCR

6(0/2/0)

ORI

#, CCR

6(0/2/0)

BSR.B

−2

13(0/2/2)

BSR.W

−2

13(0/2/2)

BSR.L

−2

13(0/2/2)

CHK

〈FEA〉, Dn (no ex)

8(0/1/0)

CHK

〈FEA〉, Dn (ex)

−2

42(2/2/6)

CHK2 (Save)

〈FEA〉, Dn (no ex)

3(0/1/0)

CHK2 (Op)

〈FEA〉, Dn (no ex)

18(X/0/0)

CHK2 (Save)

〈FEA〉, Dn (ex)

3(0/1/0)

CHK2 (Op)

〈FEA〉, Dn (ex)

−2

52(X

+ 2/1/6)

JMP

〈CEA〉

−2

6(0/2/0)

JSR

〈CEA〉

−2

13(0/2/2)

LEA

〈CEA〉, An

2(0/1/0)

LINK.W

An, #

10(0/2/2)

LINK.L

An, #

10(0/3/2)

NOP

2(0/1/0)

PEA

〈CEA〉

8(0/1/2)

RTD

−2

12(2/2/0)

RTR

−2

14(3/2/0)

RTS

−2

12(2/2/0)

UNLK

9(2/1/0)

X = There is one bus cycle for byte and word operands and two bus cycles for long-word

operands. For long-word bus cycles, add two clocks to the tail and to the number of

cycles.

NOTE: The CHK2 instruction involves a save step which other instructions do not have. To

calculate the total instruction time, calculate the save, the EA, and the operation

execution times, and combine in the order listed using the equations given in 5.7.1.6

Instruction Execution Time Calculation.

Freescale Semiconductor, Inc.

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