MC68340 datasheet(227/441 Pages) FREESCALE

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5- 90

MC68340 USER’S MANUAL

MOTOROLA

The bus controller and microsequencer operate concurrently. The bus controller can

perform a read or write or schedule a prefetch while the microsequencer controls EA

calculation or sets condition codes.

The microsequencer can also request a bus cycle that the bus controller cannot perform

immediately. When this happens, the bus cycle is queued, and the bus controller runs the

cycle when the current cycle is complete.

MICROSEQUENCER AND CONTROL

CONTROL STORE

CONTROL LOGIC

INSTRUCTION PIPELINE

STAGE

EXECUTION UNIT

PROGRAM

COUNTER

SECTION

DATA

SECTION

WRITE-PENDING

BUFFER

PREFETCH

CONTROLLER

MICROBUS

CONTROLLER

ADDRESS

BUS

DATA

BUS

BUS CONTROL

SIGNALS

Figure 5-30. Block Diagram of Independent Resources

5.7.1.3.1 Prefetch Controller. The instruction prefetch controller receives an initial

request from the microsequencer to initiate prefetching at a given address. Subsequent

prefetches are initiated by the prefetch controller whenever a pipeline stage is invalidated,

either through instruction completion or through use of extension words. Prefetch occurs

as soon as the bus is free of operand accesses previously requested by the

microsequencer. Additional state information permits the controller to inhibit prefetch

requests when a change in instruction flow (e.g., a jump or branch instruction) is

anticipated.

In a typical program, 10 to 25 percent of the instructions cause a change of flow. Each

time a change occurs, the instruction pipeline must be flushed and refilled from the new

instruction stream. If instruction prefetches, rather than operand accesses, were given

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