NB2308AI3DR2G datasheet(3/12 Pages) ONSEMI

tên linh kiện	NB2308AI3DR2G

Giải thích chi tiết về linh kiện	3.3 V Zero Delay Clock Buffer

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NB2308A

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Figure 2. Pin Configuration

VDD

REF

CLKA1

CLKA2

GND

FBK

CLKA4

CLKA3

NB2308A

VDD

CLKB1

CLKB2

CLKB4

CLKB3

GND

Table 3. PIN DESCRIPTION

Pin #

Pin Name

Description

REF (Note 3)

Input reference frequency, 5 V tolerant input.

CLKA1 (Note 4)

Buffered clock output, Bank A.

CLKA2 (Note 4)

Buffered clock output, Bank A.

VDD

3.3 V supply.

GND

Ground.

CLKB1 (Note 4)

Buffered clock output, Bank B.

CLKB2 (Note 4)

Buffered clock output, Bank B.

S2 (Note 5)

Select input, bit 2.

S1 (Note 5)

Select input, bit 1.

CLKB3 (Note 4)

Buffered clock output, Bank B.

CLKB4 (Note 4)

Buffered clock output, Bank B.

GND

Ground.

VDD

3.3 V supply.

CLKA3 (Note 4)

Buffered clock output, Bank A.

CLKA4 (Note 4)

Buffered clock output, Bank A.

FBK

PLL feedback input.

3. Weak pulldown.

4. Weak pulldown on all outputs.

5. Weak pullup on these inputs.

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