
SCG9864
8-BIT MICROCONTROLLER
Score Concept Semiconductor Ltd.
5
Sept 2000
Interrupt Mask Flag (I)
The flag will be set to 1 when entering an interrupt service routine. By that
time, all other interrupt events will be pending.
After exiting from the interrupt service routine, this interrupt mask flag will be
cleared to 0. Then interrupt handling will be resumed.
Memory
There are 64K bytes internal ROM with each page size is 16K bytes. Regarding the instruction
pointer, it is organized as iPAGE:PC for instruction fetch.
Change of program flow between pages is by modifying the PAGE register and then followed
by executing a JMP or CALL instruction. These two instructions will load the PAGE register to
iPAGE and change the content in PC for long JMP or CALL instruction. It does not need to
change the PAGE register if it is a short JMP/CALL (JMP/CALL within page) because the
PAGE register is normally the same as the iPAGE register. To exit a subroutine, long or short
return type must be specified for long or short CALL respectively.
The microcontroller has 128 bytes internal RAM data storage of address $80-$FF. This area
includes stack frame and data memory. The stack frame is usually initialized at the highest
RAM address location, i.e. $FF.
Oscillation Circuits
Main system and subsystem oscillation circuitry generates the internal clock signal for the
CPU and other hardware timings. The main system clock uses the RC oscillation source. The
operating frequency is up to 4 MHz. This clock is for the CPU and the two timers.
The subsystem clock is for the real time signals. It uses 32.768 kHz crystal. It has to be tied to
a voltage level, either HIGH or LOW, if the real time timer and the watch dog timer are not
used.
Power Down
The microcontroller supports power down mode for saving power.
Executing a STOP instruction will stop the main system oscillation to save most of
microcontroller power.
Only an external interrupt will release the microcontroller from STOP mode.
Interrupts
The MICROCONTROLLER has 2 timer interrupts, one real time interrupt, one external event
interrupt and one software interrupt. When interrupt occurs, the content of PC, iPAGE and PS
are pushed onto the stack in sequence. And then, the corresponding interrupt vector is loaded
into iPAGE:PC. Upon executing a RTI instruction, the registers are popped out of the stack in
the reversed order.
The preference of interrupt priority is Timer 0 / RTC interrupt, Timer 1 interrupt and then
external interrupt.