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SCG9864
8-BIT MICROCONTROLLER
Score Concept Semiconductor Ltd.
13
Sept 2000
INTR
Bit
7654
321
0
R/W
-
----
W
W
W
Figure 15. Interrupt Control Register
TFLAG
Bit
7654
321
0
R/W
-
---
R
R
R
R
Figure 16. Timer Flag Status Register/Watch-dog Reset
0 : T0 not overflow
1 : T0 overflow
0 : T1 not overflow
1 : T1 overflow
0 : not half second
1 : half second
CLK32I Input
Reserved
Note :
Read will reset all flags.
Any write operation to TFLAG will reset the
watch dog timer.
T0/RTC (half second) interrupt
0 : disable
1 : enable
T1 interrupt
0 : disable
1 : enable
External interrupt
0 : disable
1 : enable
Reserved