FXPS7115D4 datasheet(51/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Bit

Symbol

ASICWLOT_H[7:0]

Reset

N/A

Access

Table 100. ASICWLOT_H Register (address D1h) bit allocation

7.7.28 USERDATA_0 to USERDATA_E - user data registers

User data registers are user programmable OTP registers that contain user-specific information. These

registers are included in the user programmed OTP array error detection. These registers are readable and

writable in SPI mode or I2C mode when ENDINIT is not set.

7.7.29 USERDATA_10 to USERDATA_1E - user data registers

User data registers are user programmable OTP registers that contain user-specific information. These

registers are included in the user programmed OTP array error detection. These registers are readable and

writable in SPI mode or I2C mode when ENDINIT is not set.

7.7.30 Lock and CRC Registers

The lock and CRC Registers are automatically programmed OTP registers that include the lock bit, the block

identifier, and the block OTP array CRC use for error detection. These registers are automatically programmed

when the corresponding data array is programmed to OTP using the Write OTP Enable register.

Location

Bit

Address

5Fh

CRC_UF2

LOCK_UF2

CRC_UF2[3:0]

Factory Default

AFh

CRC_F_A

LOCK_F_A

REGA_BLOCKID[2:0]

CRC_F_A[3:0]

Factory Default

varies

BFh

CRC_F_B

LOCK_F_B

REGB_BLOCKID[2:0]

CRC_F_B[3:0]

Factory Default

varies

CFh

CRC_F_C

LOCK_F_C

REGC_BLOCKID[2:0]

CRC_F_C[3:0]

Factory Default

varies

DFh

CRC_F_D

LOCK_F_D

REGD_BLOCKID[2:0]

CRC_F_D[3:0]

Factory Default

varies

EFh

CRC_F_E

LOCK_F_E

REGE_BLOCKID[2:0]

CRC_F_E[3:0]

Factory Default

FFh

CRC_F_F

LOCK_F_F

REGF_BLOCKID[2:0]

CRC_F_F[3:0]

Factory Default

Table 101. Lock and CRC Register bit definitions

7.7.31 Reserved registers

A register read command to a reserved register or a register with reserved bits results in a valid response. The

data for reserved bits may be '0' or '1'.

A register write command to a reserved register or a register with reserved bits executes and results in a valid

response. The data for the reserved bits may be '0' or '1'. A write to the reserved bits must always be '0' for

normal device operation and performance.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6.2 — 28 June 2023

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