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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

I2C DC Electrical Specifications

Note that the ADS and ID pins will all run off the core (1.2V) power supply, and these pins are required to be fixed during operation. Thus, these pins

must be statically tied to the 1.2V supply or GND.

Tables 12 through 14 below list the SDA and SCL electrical specifications for F/S-mode I2C devices.

At recommended operating conditions with VDD3 = 3.3V ± 5%

At recommended operating conditions with VDD3 = 2.5V ± 100mV

Parameter

Symbol

Minimum

Maximum

Unit

Input high voltage level

VIH

0.7 x VDD3

VDD3 (MAX)+ 0.5

V

Input low voltage level

VIL

-0.5

0.3 x VDD3

V

Hysteresis of Schmitt trigger inputs:

Vhys

0.05 x VDD3

-

Low level output voltage

VOL

00.4

V

Output fall time from VIH(MIN) to VIL(MAX) with a bus

capacitance from 10pF to 400pF

tOF

20 + 0.1 x Cb

250

ns

Pulse width of spikes which must be suppressed by

the input filter

tSP

050

ns

Input current each I/O pin (input voltage is between

0.1 x VDD3 and 0.9 x VDD3 (MAX) )

II

-10

10

uA

Capacitance for each I/O pin

CI

-10

pF

Table 12 I2C SDA & SCL DC Electrical Specifications

Parameter

Symbol

Minimum

Maximum

Unit

Input high voltage level

VIH

0.7 x VDD3

VDD3 (MAX)+ 0.1

V

Input low voltage level

VIL

-0.5

0.3 x VDD3

V

Hysteresis of Schmitt trigger inputs:

Vhys

0.05 x VDD3

-

-

Low level output voltage

VOL

00.4

V

Output fall time from VIH(MIN) to VIL(MAX) with a bus

capacitance from 10pF to 400pF

tOF

20 + 0.1 x Cb

250

ns

Pulse width of spikes which must be suppressed by

the input filter

tSP

050

ns

Input current each I/O pin (input voltage is between

0.1 x VDD3 and 0.9 x VDD3 (MAX) )

II

-10

10

uA

Capacitance for each I/O pin

CI

-10

pF

Table 13 I2C SDA & SCL DC Electrical Specifications