Features
u Interfaces - sRIO
– 40 bidirectional serial RapidIO (sRIO) lanes v 1.3
– Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps
– All lanes support short haul or long haul reach for each PHY speed
– Configurable port count to up to 16 ports
– Two enhanced quads can be configured as 4 1x ports or 1 4x ports
– Supports standard 4 levels of priority
– Error handling support: It allows error detection, logging and
response from all major functional blocks on the device.
u Interfaces - I2C
– Provides I2C port for maintenance and error reporting
– Master or Slave Operation
– Master allows power-on configuration from external ROM
– Master mode configuration with external image compressing and
checksum
u Performance
– 100 Gbps of peak switching bandwidth
– Non-blocking data flow architecture within each sRIO priority
– low latency for all packet length and load condition
– Internal queuing buffer and retransmit buffer
– Standard receiver based physical layer flow control
u Features
– Configurable for cut-thru and store-and-forward modes
– Device configurable through any of sRIO ports, I2C, or JTAG
– Packet Trace function: It allows copying or filtering packets on a perport
basis. Each port provides the ability to match the first 160 bits of
any packet against up to 4 programmable comparison values to copy
the packet to a programmable output trace port or drop it.
– Supports up to 40 simultaneous multicast masks per each port
– Support Broadcast
– Port Loopback Debug Feature
– Software assisted error recovery, supporting hot swap
– Ports may be individually turned off to reduce power
– PMON counters for monitor and diagnostics per port
– Serdes physical diagnostic registers
– Embedded PRBS generation and detection with programmable polynomial
cover error rate under all conditions
– 0.13um technology
– Low power dissipation
– Full JTAG Boundary Scan support (IEEE1149.1 & 1149.6)
– Package: FCBGA 676-ball grid array, 27mm x 27mm, 1.0mm ball pitch