S71GS256 datasheet(171/195 Pages) SPANSION

171 / 195 page

October 4, 2004 cellRAM_00_A0

CellularRAM Type 2

171

Ad vance

Info rmat i o n

Asynchronous WRITE Operation

The timing parameters provided in Figure 33 require that all WRITE operations

must be completed within 4µs. After completing a WRITE operation, the device

must either enter standby (by transitioning CE# HIGH), or else perform a second

operation (READ or WRITE) using a new address. Figure 61 and Figure 62 dem-

onstrate these constraints as they apply during an asynchronous (page-mode-

disabled) operation. Either the CE# active period (tCEM in Figure 61) or the ad-

dress valid period (tTM in Figure 62) must be less than 4µs during any WRITE

operation, otherwise, the extended WRITE timings must be used.

Extended WRITE Timing— Asynchronous WRITE Operation

Modified timings are required during extended WRITE operations (see Figure 63).

An extended WRITE operation requires that both the write pulse width (tWP) and

the data valid period (tDW) be lengthened to at least the minimum WRITE cycle

time (tWC [MIN]). These increased timings ensure that time is available for both

a refresh operation and a successful completion of the WRITE operation.

Figure 61. Extended Timing for tCEM

Figure 62. Extended Timing for tTM

Table 64. Extended Cycle Impact on READ and WRITE Cycles

Page Mode

Timing Constraint

Read Cycle

Write Cycle

Asynchronous

Page Mode Disabled

tCEM and tTM > 4µs

(See Figure 61 and Figure 62.)

No impact.

Must use extended WRITE

timing.

(See Figure 62)

Asynchronous

Page Mode Enabled

tCEM > 4µs

(See Figure 61.)

All following intrapage READ

access times are tAA (not tAPA).

Must use extended WRITE

timing.

(See Figure 63)

Burst

tCEM > 4µs (See Figure 61.)

Burst must cross a row boundary within 4µs.

CE#

ADDRESS

tCEM

4µs

CE#

ADDRESS

TM<

4µs

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