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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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MPC850DSL bảng dữ liệu(PDF) 52 Page - Freescale Semiconductor, Inc |
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MPC850DSL bảng dữ liệu(HTML) 52 Page - Freescale Semiconductor, Inc |
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52 / 72 page  MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 52 Freescale Semiconductor CPM Electrical Characteristics 8.6 SCC in NMSI Mode Electrical Specifications Table 18 provides the NMSI external clock timing. Table 19 provides the NMSI internal clock timing. Table 18. NMSI External Clock Timing Num Characteristic All Frequencies Unit Min Max 100 RCLKx and TCLKx frequency 1 (x = 2, 3 for all specs in this table) 1 The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater than or equal to 2.25/1. 1/SYNCCLK — ns 101 RCLKx and TCLKx width low 1/SYNCCLK +5 — ns 102 RCLKx and TCLKx rise/fall time — 15.00 ns 103 TXDx active delay (from TCLKx falling edge) 0.00 50.00 ns 104 RTSx active/inactive delay (from TCLKx falling edge) 0.00 50.00 ns 105 CTSx setup time to TCLKx rising edge 5.00 — ns 106 RXDx setup time to RCLKx rising edge 5.00 — ns 107 RXDx hold time from RCLKx rising edge 2 2 Also applies to CD and CTS hold time when they are used as an external sync signal. 5.00 — ns 108 CDx setup time to RCLKx rising edge 5.00 — ns Table 19. NMSI Internal Clock Timing Num Characteristic All Frequencies Unit Min Max 100 RCLKx and TCLKx frequency 1 (x = 2, 3 for all specs in this table) 1 The ratios SyncCLK/RCLKx and SyncCLK/TCLK1x must be greater or equal to 3/1. 0.00 SYNCCLK/3 MHz 102 RCLKx and TCLKx rise/fall time — — ns 103 TXDx active delay (from TCLKx falling edge) 0.00 30.00 ns 104 RTSx active/inactive delay (from TCLKx falling edge) 0.00 30.00 ns 105 CTSx setup time to TCLKx rising edge 40.00 — ns 106 RXDx setup time to RCLKx rising edge 40.00 — ns 107 RXDx hold time from RCLKx rising edge 2 2 Also applies to CD and CTS hold time when they are used as an external sync signals. 0.00 — ns 108 CDx setup time to RCLKx rising edge 40.00 — ns |
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