GLT6400L08LL-85ST datasheet(5/10 Pages) ETC

5 / 10 page

G -LINK

GLT6400L08

Ultra Low Power 512k x 8 CMOS SRAM

Feb 2001(Rev. 1.1)

G-Link Technology Corporation

2701 Northwestern Parkway

Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based

Industrial Park, Hsin Chu, Taiwan.

- 5 -

Data Retention Waveform

Data Retention Mode

Vcc

VDR

VDR >= 1.0V

tCDR

2.7V

VIH

AC Test Conditions

AC Test Loads and Waveforms

CL*

TTL

Output Load Condition

*Including Scope and Jig Capacitance

CL = 30pf + 1TTL Load

Read Cycle

(3,9)( 70ns Vcc=3V to 3.6V , 85ns Vcc=2.7V to 3.3V )

Unit Note

Parameter

Symbol

Min

Max

Min

Max

Read Cycle Time

tRC

Address Access Time

tAA

Chip Enable Access Time

tACE

Output Enable Access Time

tOE

Output Hold from address Change

tOH

Chip Enable to Output in Low-Z

tCLZ

4,5

Chip Disable to Output in High-Z

tCHZ

4,5

Output Enable to Output in Low-Z

tOLZ

4,5

Output Disable to Output in High-Z

tOHZ

4,5

Power-Up Time

tPU

Power-Down Time

tPD

Input Pulse Levels

0.4V to 2.4V

Input Rise and Fall Time

Input and Output Timing

Reference Level

5 ns

1.4V

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