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PIC18F6410E/PTSQTP bảng dữ liệu(PDF) 27 Page - Microchip Technology |
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PIC18F6410E/PTSQTP bảng dữ liệu(HTML) 27 Page - Microchip Technology |
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27 / 404 page ![]() 2004 Microchip Technology Inc. Preliminary DS39635A-page 25 PIC18F6310/6410/8310/8410 PORTE is a bidirectional I/O port. RE0/AD8/RD RE0 AD8 RD 4 I/O I/O I ST TTL TTL Digital I/O. External memory address/data 8. Read control for Parallel Slave Port. RE1/AD9/WR RE1 AD9 WR 3 I/O I/O I ST TTL TTL Digital I/O. External memory address/data 9. Write control for Parallel Slave Port. RE2/AD10/CS RE2 AD10 CS 78 I/O I/O I ST TTL TTL Digital I/O. External memory address/data 10. Chip Select control for Parallel Slave Port. RE3/AD11 RE3 AD11 77 I/O I/O ST TTL Digital I/O. External memory address/data 11. RE4/AD12 RE4 AD12 76 I/O I/O ST TTL Digital I/O. External memory address/data 12. RE5/AD13 RE5 AD13 75 I/O I/O ST TTL Digital I/O. External memory address/data 13. RE6/AD14 RE6 AD14 74 I/O I/O ST TTL Digital I/O. External memory address/data 14. RE7/CCP2/AD15 RE7 CCP2(3) AD15 73 I/O I/O I/O ST ST TTL Digital I/O. Capture 2 input/Compare 2 output/PWM 2 output. External memory address/data 15. TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). |
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