TMPR4955AF datasheet(149/168 Pages) TOSHIBA

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Chapter 8 TX4955A Processor Interrupts

8-1

Chapter 8.

TX4955A Processor Interrupts

Four types of interrupt are available on the TX4955A. These are:

•

one non-maskable interrupt, NMI

•

six external interrupts

•

two software interrupts

•

one timer interrupt

These are described in this chapter.

8.1

Nonmaskable Interrupt

The non-maskable interrupt is signaled by asserting the NMI

NMI

NMI* pin (low), forcing the processor

to branch to the Reset Exception vector. This pin is latched into an internal register by the

rising edge of SClock

SClock

SClock, as shown in Figure 8.4.1. An NMI can also be set by an external write

through the SysAD

SysAD

SysAD bus. On the data cycle, SysAD (22)

SysAD (22)

SysAD (22) acts as the write enable for SysAD (6)

SysAD (6)

SysAD (6),

which is the value to be written as the interrupt.

NMI only takes effect when the processor pipeline is running. Thus NMI can be used to

recover the processor from a software hang (for example, in an infinite loop) but cannot be used

to recover the processor from a hardware hang (for example, no read response from an external

agent). NMI cannot cause drive contention on the SysAD

SysAD

SysAD bus and no reset of external agents is

required.

This interrupt cannot be masked.

The NMI

NMI

NMI* pin is latched by the rising edge of SClock

SClock

SClock, however the NMI exception occurs in

response to the falling edge of the NMI

NMI

NMI* signal, and is not level-sensitive.

Figure 8.4.1 shows the internal derivation of the NMI

NMI

NMI signal. The NMI

NMI

NMI* pin is latched into an

internal register by the rising edge of SClock

SClock

SClock. Bit 6 of the Interrupt register is then ORed with

the inverted value of NMI

NMI

NMI* to form the nonmaskable interrupt.

8.2

External Interrupts

External interrupts are set by asserting the external interrupt pins Int

Int

Int ((((5555:0)

:0)

:0)*. They also may

be set by an external write through the SysAD

SysAD

SysAD bus. During the data cycle, SysAD (2

SysAD (2

SysAD (21111:16)

:16)

:16) are

the write enables for bits SysAD (

SysAD (

SysAD (5555:0)

:0)

:0), which are the values to be written as interrupts.

These interrupts can be masked with the

IM, IE, and EXL fields of the Status register.

Note: Int5* is doubled as a Timer Interrupt. Therefore either is selected with the External pin (TintDis).

8.3

Software Interrupt

Software interrupts use bits 1 and 0 of the interrupt pending,

IP, field in the Cause register.

These may be written by software, but there is no hardware mechanism to set or clear these

bits.

These interrupts are maskable.

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