TMPR4955AF datasheet(56/168 Pages) TOSHIBA

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Chapter 3 Initialization Interface

3-6

3.3.4

Reverse Endianness

When the

RE bit in the Status register is set, endianess as seen by user software is

reversed from its previous state.

3.3.5

Instruction Trace Support

Consists of an Enhanced JTAG Module and a Debug Support Unit (DSU). It can be used

to provide single-step execution and hardware break-points for debugging processor system.

EJTAG utilizes JTAG interface and extends the ability to access the inside register

contents, host system peripherals, and system memory.

3.3.6

Bootstrap Exception Vector

This bit is used when diagnostic tests cause exceptions to occur prior to verifying proper

operation of the cache and main memory system.

When set, the Bootstrap Exception Vector (

BEV) bit in the Status register causes the

TLB refill exception vector to be relocated to a virtual address of 0xFFFF FFFF BFC0 0200

and the general exception vector relocated to address 0xFFFF FFFF BFC0 0380.

When

BEV is cleared, these vectors are located at 0xFFFF FFFF 8000 0000 (TLB refill)

and 0xFFFF FFFF 8000 0180 (general).

3.3.7

Interrupt Enable

When IE bit is clear, interrupts are not allowed, with the exception of reset and the

nonmaskable interrupt.

3.3.8

Floating-Point Reigsters

By setting the FR bit in the Status register, the user accesses the full set of 32, 64-bit

floating point registers as defined in the MIPS III ISA. When reset, the processor accesses

the registers as defined in the MIPS II architecture.

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