TMPR4955AF datasheet(61/168 Pages) TOSHIBA

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Chapter 5 Cache Organization

5-1

Chapter 5

Cache Organization

This chapter describes in detail the cache memory: its place in the TX4955A memory

organization, and individual organization of the caches.

This chapter uses the following terminology:

•

The data cache may also be referred to as the D-cache.

•

The instruction cache may also be referred to as the I-cache.

These terms are used interchangeably throughout this book.

5.1

Memory Organization

Figure 5.1.1 shows the TX4955A system memory hierarchy. In the logical memory hierarchy,

both primary and secondary caches lie between the CPU and main memory. They are designed

to make the speedup of memory accesses transparent to the user.

Each functional block in Figure 5.1.1 has the capacity to hold more data than the block above

it. For instance, physical main memory has a larger capacity than the caches. At the same time,

each functional block takes longer to access than any block above it. For instance, it takes

longer to access data in main memory than in the CPU on-chip registers.

TX49 CPU

CPU Core

Core

I-cache

D-cache

Caches

Cache

Increasing Data

Capacity

Faster Access

Time

Memory

Peripherals

Main Memory

Disk, CD-ROM,

Tape, etc.

Figure 5.1.1 Logical Hierarchy of Memory

The TX4955A processor has two on-chip caches: one holds instructions (the instruction cache),

the other holds data (the data cache). The instruction and data caches can be read in one PClock

PClock

cycle.

Data writes are pipelined and can complete at a rate of one per PClock

PClock

PClock cycle. In the first stage

of the cycle, the store address is translated and the tag is checked; in the second stage, the data

is written into the data RAM.

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