TMPR4955AF datasheet(139/168 Pages) TOSHIBA

139 / 168 page

Chapter 7 JTAG Interface

7-5

7.3.3

Boundary-Scan Register

The

Boundary Scan register includes all of the inputs and outputs of the TX4955A

processor, except some clock and phase lock loop signals. The pins of the TX4955A chip can

be configured to drive any arbitrary pattern by scanning into the

Boundary Scan register

from the Shift-DR state. Incoming data to the processor is examined by shifting while in the

Capture-DR state with the

Boundary Scan register enabled.

The

Boundary-scan register is a single, 87-bit-wide, shift register-based path containing

cells connected to all input and output pads on the TX4955A processor. Figure 7.3.4 shows

the

Boundary-scan register.

See Table 7.3.2

SysEN1

Figure 7.3.4 Format of the Boundary-scan Register

The most-significant bit, SysEN (bit3 to bit0), are the JTAG output enable bit for all

outputs of the processor. Output is enabled when those bit are set to 1 (default state).

The remaining 83 bits correspond to 83 signal pads of the processor.

At the end of this chapter, Table 7.3.2 lists the scan order of these 89 scan bits, starting

from JTDI

JTDI

JTDI and ending with JTDO

JTDO

JTDO.

The JTDI input is loaded to the LSB of the Boundary Scan register. The MSB of the

Boundary Scan register is retrieved from the JTDO output.

7.3.4

Device Identification Register

The Device Identification register is a 32-bit shift register. It is used to read serially from

the IC the identification code indicating the IC manufacturer, part number, and version.

The following shows the Device Identification register structure.

28 27

12 11

Version

Product number

manufacturer

identification code

4 bits

16 bits

11 bits

Figure 7.3.5 Device Identification Register

The TX4955A device identification code is 0x00017031.

The device identification code is shifted out starting from the LSB.

Figure 7.3.6 Devide Identification Register shift Direction

LSB

JTDO

MSB

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