PCF5270VM100 datasheet(49/56 Pages) FREESCALE

49 / 56 page

Preliminary Electrical Characteristics

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

Freescale Semiconductor

Figure 16 shows MII transmit signal timings listed in Table 38.

Figure 16. MII Transmit Signal Timing Diagram

8.10.3 MII Async Inputs Signal Timing (ECRS and ECOL)

Table 39 lists MII asynchronous inputs signal timing.

Figure 17 shows MII asynchronous input timings listed in Table 39.

Figure 17. MII Async Inputs Timing Diagram

8.10.4 MII Serial Management Channel Timing (EMDIO and EMDC)

Table 40 lists MII serial management channel timings. The FEC functions correctly with a maximum

MDC frequency of 2.5 MHz.

Table 39. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

ECRS, ECOL minimum pulse width

1.5

—

ETXCLK period

Table 40. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10

EMDC falling edge to EMDIO output invalid (minimum propagation

delay)

0—

M11

EMDC falling edge to EMDIO output valid (max prop delay)

—

M12

EMDIO (input) to EMDC rising edge setup

—

M13

EMDIO (input) to EMDC rising edge hold

—

M14

EMDC pulse width high

40%

60%

MDC period

M15

EMDC pulse width low

40%

60%

MDC period

ETXCLK (input)

ETXD[3:0] (outputs)

ETXEN

ETXER

ECRS, ECOL

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