ICS853S031I datasheet(12/23 Pages) RENESAS

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ICS853S031I Data Sheet

LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

ICS853S031BYI REVISION A AUGUST 17, 2011

Recommendations for Unused Output Pins

Inputs:

PCLK/nPCLK Inputs

For applications not requiring the use of a differential input, both the

PCLK and nPCLK pins can be left floating. Though not required, but

for additional protection, a 1k

Ω resistor can be tied from PCLK to

ground. For applications

CLK/nCLK Inputs

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1k

Ω resistor can be tied from CLK to ground.

LVCMOS Control Pins

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1k

Ω resistor can be used.

Outputs:

LVPECL Outputs

All unused LVPECL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

Ω

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 5A and 5B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

Figure 5A. 3.3V LVPECL Output Termination

Figure 5B. 3.3V LVPECL Output Termination

3.3V

CC - 2V

Ω

RTT

o = 50Ω

RTT =

* Z

((V

OH + VOL) / (VCC – 2)) – 2

3.3V

LVPECL

Input

Ω

3.3V

125

Ω

125

Ω

o = 50Ω

LVPECL

Input

3.3V

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