ICS853S031I datasheet(11/23 Pages) RENESAS

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ICS853S031I Data Sheet

LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

ICS853S031BYI REVISION A AUGUST 17, 2011

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both VSWING and VOH must meet the VPP

and VCMR input requirements. Figures 4A to 4F show interface

examples for the CLK/nCLK input driven by the most common driver

types. The input interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the

driver termination requirements. For example, in Figure 4A, the input

termination applies for IDT open emitter LVHSTL drivers. If you are

using an LVHSTL driver from another vendor, use their termination

recommendation.

Figure 4A. CLK/nCLK Input Driven by an

IDT Open Emitter LVHSTL Driver

Figure 4C. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 4E. CLK/nCLK Input Driven by a

3.3V HCSL Driver

Figure 4B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 4D. CLK/nCLK Input Driven by a 3.3V LVDS Driver

Figure 4F. CLK/nCLK Input Driven by a 2.5V SSTL Driver

Ω

1.8V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

125

Ω

125

Ω

3.3V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVPECL

Differential

Input

HCSL

*R3

Ω

*R4

Ω

CLK

nCLK

3.3V

Zo = 50

Ω

Zo = 50

Ω

Differential

Input

Ω

*Optional – R3 and R4 can be 0

Ω

CLK

nCLK

Differential

Input

LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

Ω

3.3V

100

Ω

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

Differential

Input

SSTL

2.5V

Zo = 60

Ω

Zo = 60

Ω

2.5V

3.3V

120

Ω

120

Ω

120

Ω

120

Ω

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