ICS8516I datasheet(9/19 Pages) RENESAS

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ICS8516I REVISION B SEPTEMBER 10, 2009

ICS8516I Data Sheet

LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

APPLICATION INFORMATION

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

= 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

INPUTS:

CLK/nCLK INPUTS

For applications not requiring the use of the differential input,

both CLK and nCLK can be left floating. Though not required, but

for additional protection, a 1k

Ω resistor can be tied from CLK to

ground.

LVCMOS CONTROL PINS

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVDS OUTPUTS

All unused LVDS outputs should be terminated with 100

Ω resistor

between the differential pair.

V_REF

Single Ended Clock Input

VDD

CLK

nCLK

0.1u

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