ICS8516I datasheet(6/19 Pages) RENESAS

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ICS8516I REVISION B SEPTEMBER 10, 2009

ICS8516I Data Sheet

LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

ADDITIVE PHASE JITTER

Additive Phase Jitter @

155.52MHz (12kHz to 20MHz)

= 148fs typical

-50

-60

-70

-80

-90

-100

-120

-130

-140

-150

-160

10k

100k

10M

100M

The spectral purity in a band at a specific offset from the

fundamental compared to the power of the fundamental is called

the

dBc Phase Noise. This value is normally expressed using a

Phase noise plot and is most often the specified plot in many

applications. Phase noise is defined as the ratio of the noise power

present in a 1Hz band at a specified offset from the fundamental

frequency to the power value of the fundamental. This ratio is

expressed in decibels (dBm) or a ratio of the power in the 1Hz

As with most timing specifications, phase noise measurements

has issues relating to the limitations of the equipment. Often the

noise floor of the equipment is higher than the noise floor of the

band to the power in the fundamental. When the required offset

is specified, the phase noise is called a

dBc value, which simply

means dBm at a specified offset from the fundamental. By

investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the

entire time record of the signal. It is mathematically possible to

calculate an expected bit error rate given a phase noise plot.

device. This is illustrated above. The device meets the noise floor

of what is shown, but can actually be lower. The phase noise is

dependent on the input source and measurement equipment.

OFFSET FROM CARRIER FREQUENCY (HZ)

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