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IDT5V19EE604 bảng dữ liệu(PDF) 13 Page - Renesas Technology Corp |
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IDT5V19EE604 bảng dữ liệu(HTML) 13 Page - Renesas Technology Corp |
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13 / 30 page ![]() IDT5V19EE604 EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR CLOCK SYNTHESIZER IDT® EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR 13 IDT5V19EE604 REV M 092412 Programming the Device I2C may be used to program the IDT5V19EE604. – Device (slave) address = 7'b1101010 I2C Programming The IDT5V19EE604 is programmed through an I2C-Bus serial interface, and is an I2C slave device. The read and write transfer formats are supported. The first byte of data after a write frame to the correct slave address is interpreted as the register address; this address auto-increments after each byte written or read. The frame formats are shown in the following illustration. Framing First Byte Transmitted on I2C Bus External I2C Interface Condition Progwrite Progwrite Command Frame Writes can continue as long as a Stop condition is not sent and each byte will increment the register address. 1 0 1 0 1 0 1 MSB LSB R/W ACK from Slave R/W 0 – Slave will be written by master 1 – Slave will be read by master The first byte transmitted by the Master is the Slave Address followed by the R/W bit. The Slave acknowledges by sending a “1” bit. 7-bit slave address KEY: From Master to Slave From Master to Slave, but can be omitted if followed by the correct sequence Normally, data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can generate a separate START condition, and address another Slave address without first generating a STOP condition. From Slave to Master SYMBOLS: ACK - Acknowledge (SDAT LOW) NACK – Not Acknowledge (SDAT HIGH) SR – Repeated Start Condition S – START Condition P – STOP Condition SAddress R/W ACK Command Code ACK Register ACK Data ACK P 7-bits 0 1-bit 8-bits: xxxx xx00 1-bit 8-bits 1-bit 8-bits 1-bit |
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