MPC8347A datasheet(52/108 Pages) FREESCALE

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

PCI

Table 45 provides the PCI AC timing specifications at 33 MHz.

Figure 32 provides the AC test load for PCI.

Figure 32. PCI AC Test Load

Figure 33 shows the PCI input AC timing diagram.

Figure 33. PCI Input AC Timing Diagram

Table 45. PCI AC Timing Specifications at 33 MHz

Parameter

Symbol 1

Min

Max

Unit

Notes

Clock to output valid

tPCKHOV

—11

Output hold from Clock

tPCKHOX

2—

Clock to output high impedance

tPCKHOZ

—14

2, 3

Input setup to Clock

tPCIVKH

3.0

—

2, 4

Input hold from Clock

tPCIXKH

—

2, 4

Notes:

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI

timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock,

tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect

to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.

3. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through

the component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

tPCIVKH

CLK

Input

tPCIXKH

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