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MC68331 bảng dữ liệu(PDF) 7 Page - NXP Semiconductors |
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MC68331 bảng dữ liệu(HTML) 7 Page - NXP Semiconductors |
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7 / 32 page  MC68L300EC16/D 7 Table 6 16.78 MHz AC Timing (V DD and V DDSYN = 3.0 to 3.6Vdc, V SS = 0 Vdc, T A = T L to T H) 1 Num Characteristic Symbol Min Max Unit F1 Frequency of Operation fsys — 16.78 MHz 1 Clock Period tcyc 59.6 — ns 1A ECLK Period tEcyc 476 — ns 1B External Clock Input Period2 tXcyc 59.6 — ns 2, 3 Clock Pulse Width tCW 24 — ns 2A, 3A ECLK Pulse Width tECW 236 — ns 2B, 3B External Clock Input High/Low Time2 tXCHL 29.8 — ns 4, 5 CLKOUT Rise and Fall Time tCrf —7 ns 4A, 5A Rise and Fall Time (All outputs except CLKOUT) trf —8 ns 4B, 5B External Clock Input Rise and Fall Time tXCrf —4 ns 6 Clock High to ADDR, FC, RMC, SIZ Valid tCHAV 029 ns 7 Clock High to ADDR, Data, FC, RMC,SIZ High Impedance tCHAZx 059 ns 8 Clock High to ADDR, FC, RMC, SIZ Invalid tCHAZn 0— ns 9 Clock Low to AS, DS, CS Asserted tCLSA 025 ns 9A AS to DS or CS Asserted (Read)3 tSTSA –15 15 ns 9C Clock Low to IFETCH, IPIPE Asserted tCLIA 222 ns 11 ADDR, FC, RMC, SIZ Valid to AS, CS, (and DS Read) Asserted tAVSA 15 — ns 12 Clock Low to AS, DS, CS Negated tCLSN 229 ns 12A Clock Low to IFETCH, IPIPE Negated tCLIN 229 ns 13 AS, DS, CS Negated to ADDR, FC, SIZ Invalid (Address Hold) tSNAI 15 — ns 14 AS, CS (and DS Read) Width Asserted tSWA 100 — ns 14A DS, CS Width Asserted (Write) tSWAW 45 — ns 14B AS, CS (and DS Read) Width Asserted (Fast Cycle) tSWDW 40 — ns 15 AS, DS, CS Width Negated4 tSN 40 — ns 16 Clock High to AS, DS, R/W High Impedance tCHSZ —59 ns 17 AS, DS, CS Negated to R/W High tSNRN 15 — ns 18 Clock High to R/W High tCHRH 029 ns 20 Clock High to R/W Low tCHRL 029 ns 21 R/W High to AS, CS Asserted tRAAA 15 — ns 22 R/W Low to DS, CS Asserted (Write) tRASA 70 — ns 23 Clock High to Data Out Valid tCHDO —29 ns 24 Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle) tDVASN 15 — ns 25 DS, CS Negated to Data Out Invalid (Data Out Hold) tSNDOI 15 — ns 26 Data Out Valid to DS, CS Asserted (Write) tDVSA 15 — ns 27 Data In Valid to Clock Low (Data Setup) tDICL 5— ns 27A Late BERR, HALT Asserted to Clock Low (Setup Time) tBELCL 20 — ns 28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated tSNDN 080 ns 29 DS, CS Negated to Data In Invalid (Data In Hold)5 tSNDI 0— ns 29A DS, CS Negated to Data In High Impedance5, 6 tSHDI —55 ns 30 CLKOUT Low to Data In Invalid (Fast Cycle Hold)5 tCLDI 10 — ns 30A CLKOUT Low to Data In High Impedance5 tCLDH —90 ns 31 DSACK[1:0] Asserted to Data In Valid7 tDADI —50 ns 33 Clock Low to BG Asserted/Negated tCLBAN —29 ns 35 BR Asserted to BG Asserted (RMC not Asserted)8 tBRAGA 1— tcyc 37 BGACK Asserted to BG Negated tGAGN 12 tcyc 39 BG Width Negated tGH 2— tcyc 39A BG Width Asserted tGA 1— tcyc 46 R/W Width Asserted (Write or Read) tRWA 150 — ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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