MC68331 datasheet(18/32 Pages) NXP

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MC68L300EC16/D

Figure 15 ECLK Timing Diagram

NOTES:

1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.

2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.

3. Address access time = tEcyc – tEAD – tEDSR.

4. Chip select access time = tEcyc – tECSD – tEDSR.

Table 8 ECLK Bus Timing

and V

DDSYN

= 3.0 to 3.6Vdc, V

= 0 Vdc, T

= T

to T

Num

Characteristic

Symbol

Min

Max

Unit

ECLK Low to Address Valid2

tEAD

—60

ECLK Low to Address Hold

tEAH

—

ECLK Low to CS Valid (CS Delay)

tECSD

—

150

ECLK Low to CS Hold

tECSH

—

CS Negated Width

tECSN

—

Read Data Setup Time

tEDSR

—

Read Data Hold Time

tEDHR

5—

ECLK Low to Data High Impedance

tEDHZ

—60

CS Negated to Data Hold (Read)

tECDH

0—

E10

CS Negated to Data High Impedance

tECDZ

—1

tcyc

E11

ECLK Low to Data Valid (Write)

tEDDW

—2

tcyc

E12

ECLK Low to Data Hold (Write)

tEDHW

—

E13

Address Access Time (Read)3

tEACC

386

—

E14

Chip-Select Access Time (Read)4

tEACS

296

—

E15

Address Setup Time

tEAS

1/2

—

tcyc

68300 E CYCLE TIM

CLKOUT

ADDR[23:0]

ECLK

DATA[15:0]

E10

E12

E14

E13

DATA[15:0]

E15

E11

WRITE

READ

WRITE

R/W

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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