ICS8S73034I Data Sheet

LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER

ICS8S73034AMI REVISION A JUNE 8, 2011

2

©2011 Integrated Device Technology, Inc.

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Function Table

Table 3. Truth Table

↑ = Rising edge transition

↓ = Falling edge transition

X = Don’t care

Number

Name

Type

Description

1, 2

Q0, nQ0

Output

Differential output pair. LVPECL interface levels.

3, 6, 16

VCC

Power

Power supply pins.

4, 5

Q1, nQ1

Output

Differential output pair. LVPECL interface levels.

7, 8

Q2, nQ2

Output

Differential output pair. LVPECL interface levels.

9VEE

Power

Negative supply pin.

10

MR

Input

Pulldown

Active High Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs Qx to go low and the inverted outputs nQx to go high.

When logic LOW, the internal dividers and the outputs are enabled.

LVCMOS/LVTTL interface levels.

11

VBB

Output

Bias voltage.

12

nPCLK

Input

Pullup/

Pulldown

Inverting differential clock input. Defaults to 2/3 * VCC when left open.

LVPECL interface levels.

13

PCLK

Input

Pulldown

Non-inverting differential clock input. LVPECL interface levels.

14

nc

Unused

No connect.

15

nEN

Input

Pulldown

Synchronous clock enable. When logic LOW, the clock is enabled and

frequency-divided. When logic HIGH, the clock is disabled and the outputs remain

stopped in the same logic state (hold). LVTTL / LVCMOS interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

RPULLDOWN

Input Pulldown Resistor

75

k

Ω

RPULLUP

Input Pullup Resistor

37.5

k

Ω

Inputs

Function

PCLK

nEN

MR

↓

L

L

Divide

↑

H

L

Hold Q[0:2]

X

X

H

Reset Q[0:2]