LP3972 datasheet(49/59 Pages) NSC

49 / 59 page

LP3972 Controls (Continued)

WAKE-UP FUNCTIONALITY (PWR_ON, nTEST_JIG,

SPARE AND EXT_WAKEUP)

Three input pins can be used to assert wakeup output for 10

ms for application processor notification to wakeup. SPARE

Input can be programmed through I

2C compatible interface

to be active low or high (SPARE bit, Default is active low ‘1’).

A reason for wakeup event can be read through I

2C compat-

ible interface also. Additionally wakeup inputs have 30 ms

de-bounce filtering. Furthermore PWR_ON have distinguish-

ing between short and long (

∼1s) pulses (push button input).

LP3972 also has an internal Thermal Shutdown early warn-

ing that generates a wakeup to the system also. This is

generated usually at 125˚C.

20207619

WAKEUP register bits

Reason for WAKEUP

WUP0

SPARE

WUP1

TEST_JIG

WUP2

PWR_ON short pulse

WUP3

PWR_ON long pulse

TSD_EW

TSD Early Warning

INTERNAL THERMAL SHUTDOWN PROCEDURE

Thermal shutdown is build to generate early warning (typ.

125˚C) which triggers the EXT_WAKEUP for the processor

acknowledge. When a thermal shutdown triggers (typ.

160˚C) the PMU will reset the system until the device cools

down.

BATTERY SWITCH AND BACK UP BATTERY CHARGER

When Back-Up battery is connected but the main battery has

been removed or its supply voltage too low, LP3972 uses

Back-Up Battery for generating LDO_RTC voltage. When

Main Battery is available the battery fet switches over to the

main battery for LDO_RTC voltage. When Main battery volt-

age is too low or removed nBATT_FLT is asserted. If no back

up battery exists, the battery switch to back up can be

switched off by nBU_BAT_EN bit. User can set the battery

fault determination voltage and battery charger current via

2C compatible interface. Enabling of back up battery

charger can be done via serial interface (nBAT_CHG_EN) or

external charger enable pin (nCHG_EN). Pin 29 is set as

external charger enable input by default.

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