LP3972 datasheet(24/59 Pages) NSC

24 / 59 page

2C Compatible Interface (Continued)

LP3972 CONTROL REGISTER

Read/Write

8h’07

SCR

R/W

System Control Register

8h’10

OVER1

R/W

Output Voltage Enable Register 1

8h’11

OVSR1

Output Voltage Status Register 1

8h’12

OVER2

R/W

Output Voltage Enable Register 2

8h’13

OVSR2

Output Voltage Status Register 2

8h’20

CC1

R/W

Voltage Change Control Register 1

8h’23

ADTV1

R/W

BUCK1 Target Voltage 1 Register

8h’24

ADTV2

R/W

BUCK1 DVM Target Voltage 2 Register

8h’25

AVRC

R/W

CC_APPS Voltage Ramp Control

8h’26

CDTC1

Dummy Register

8h’27

CDTC2

Dummy Register

8h’29

SDTV1

R/W

LDO5 Target Voltage 1

8h’2A

SDTV2

R/W

LDO5 Target Voltage 2

8h’32

MDTV1

R/W

LDO1 Target Voltage 1 Register

8h’33

MDTV2

R/W

LDO1 Voltage 2 Register

8h’39

L2VCR

R/W

LDO2 Voltage Control Registers

8h’3A

L34VCR

R/W

LDO3 & LDO4 Voltage Control Registers

8h’80

SCR1

R/W

System Control Register 1

8h’81

SCR2

R/W

System Control Register 2

8h’82

OEN3

R/W

Output Voltage Enable Register 3

8h’83

OSR3

R/W

Output Voltage Status Register 3

8h’84

LOER4

R/W

Output Voltage Enable Register 3

8h’85

B2TV

R/W

CC_Buck2 Target Voltage

8h’86

B3TV

R/W

CC_Buck3 Target Voltage

8h’87

B32RC

R/W

Buck 32 Voltage Ramp Control

8h’88

ISRA

Interrupt Status Register A

8h’89

BCCR

R/W

Backup Battery Charger Control Register

8h’8E

II1RR

Internal 1 Revision Register

8h’8F

II2RR

Internal 2 Revision Register

SERIAL INTERFACE REGISTER SELECTION CODES (Bold face voltages are default values)

System Control Status Register

Register is an 8 bit register which specifies the control bits for the PMIC clocks. This register works in conjunction with the SYNC

pin where an external clock PLL buffer operating at 13 MHz is synchronized with the oscillators of the buck converters.

System Control Register (SCR) 8h’07

Bit

7654321

Designation

Reserved

CLK_SCL

Reset Value

00000

System Control Register (SCR) 8h’07 Definitions

Bit

Access

Name

Description

7-1

—

Reserved

R/W

CLK_SCL

External Clock Select

0 = Internal Oscillator clock for Buck Converters

1 = External 13 MHz Oscillator clock for Buck Converters

LP3972 bảng dữ liệu(PDF) 24 Page - National Semiconductor (TI)

LP3972 bảng dữ liệu(HTML) 24 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

bảng dữ liệu tải về

Link URL