604 Hardware Specifications

7

Preliminary/Subject to Change without Notice

20

SYSCLK to ARTRY and SHD precharge

enable

—

0.5*

tsysclk

+

0.75

—

0.5*

tsysclk

+

0.75

—

0.5*

tsysclk

+

0.75

ns

3

21

Maximum delay to ARTRY and SHD

precharge

—

1.5*

tsysclk

—

1.5*

tsysclk

—

1.5*

tsysclk

ns

3

22

SYSCLK to ARTRY and SHD high

impedance after precharge

—

2.0*

tsysclk

—

2.0*

tsysclk

—

2.0*

tsysclk

ns

3

Rise time (ARTRY, SHD, ABB, DBB, TS,

and XATS)

1.0

1.0

1.0

ns

4

Rise time (all signals except ARTRY,

SHD, ABB, DBB, TS, and XATS)

1.0

1.0

1.0

ns

4

Fall time (ARTRY, SHD, ABB, DBB, TS,

and XATS)

1.0

1.0

1.0

ns

4

Fall time (all signals except ARTRY, SHD,

ABB, DBB, TS, and XATS)

1.0

1.0

1.0

ns

4

Notes:

1. These values are guaranteed by design, and are not tested.

2. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external

voltage from 5.5 V to 0.8 V instead of from 3.6 V to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS

levels).

3. t

sysclk

is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as

t

sysclk

the numbers given in the table must be multiplied by the period of SYSCLK to compute the actual

time duration (in nanoseconds) of the parameter in question.

4. These specifications are nominal values.

Table 7. PowerPC 604 Microprocessor Output AC Timing Specifications (Continued)

Vdd = 3.3

± 5% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ Tj ≤ 105 °C

Num

Characteristic

100 MHz

120 MHz

133 MHz

Unit

Notes

Min

Max

Min

Max

Min

Max

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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