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PowerPC 602 RISC Microprocessor Hardware Specifications

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Facilities for enhanced system performance

— A 64-bit (address and data multiplexed) external data bus with burst transfers

— Support for injected snoops by other devices during ownership of bus tenure

— Ability to broadcast a line-fill address, during the address tenure of a writeback transaction on

the bus

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Integrated power management

— Low-power 3.3-volt design

— Internal processor/bus clock multiplier that provides 2/1 and 3/1 ratios

— Three static power-saving modes—doze, nap, and sleep

— Automatic dynamic power reduction when internal functional units are idle

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Data bus externally selectable as either 32 or 64 bits

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In-system testability and debugging features through JTAG port

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Three power saving modes

— Doze—All the functional units of the 602 are disabled except for the time base/decrementer

registers and the bus snooping logic. When the processor is in doze mode, an external

asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft

reset, or machine check brings the 602 into the full-power state. The 602 in doze mode

maintains the PLL in a fully-powered state and locked to the system external clock input

(SYSCLK) so a transition to the full-power state takes only a few processor clock cycles.

— Nap—The nap mode further reduces power consumption by disabling bus snooping, leaving

only the time base register and the PLL in a powered state. The 602 returns to the full-power

state upon receipt of an external asynchronous interrupt, a system management interrupt, a

decrementer exception, a hard or soft reset, or a machine check input (MCP). A return to full-

power state from a nap state takes only a few processor clock cycles.

— Sleep—Sleep mode reduces power consumption to a minimum by disabling all internal

functional units, after which external system logic may disable the PLL and SYSCLK.

Returning the 602 to the full-power state requires the enabling of the PLL and SYSCLK,

followed by the assertion of an external asynchronous interrupt, a system management

interrupt, a hard or soft reset, or a machine check input (MCP) signal after the time required to

relock the PLL.

Freescale Semiconductor, Inc.

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