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MPC603 bảng dữ liệu(PDF) 21 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  PowerPC™ 603 RISC Microprocessor Technical Summary
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PowerPC 603 RISC Microprocessor Technical Summary
21
Table 2. Exceptions and Conditions
Exception
Type
Vector Offset
(hex)
Causing Conditions
Reserved
00000
—
System reset
00100
A system reset is caused by the assertion of either SRESET or HRESET.
Machine check
00200
A machine check is caused by the assertion of the TEA signal during a data bus transaction,
assertion of MCP, or an address or data parity error.
DSI
00300
The cause of a DSI exception can be determined by the bit settings in the DSISR, listed as
follows:
1 Set if the translation of an attempted access is not found in the primary hash table entry
group (HTEG), or in the rehashed secondary HTEG, or in the range of a DBAT register;
otherwise cleared.
4 Set if a memory access is not permitted by the page or DBAT protection mechanism;
otherwise cleared.
5 Set if the access was to an I/O segment (SR[T] =1) by an eciwx, ecowx, lwarx, or
stwcx. instruction; otherwise cleared.
6 Set for a store operation and cleared for a load operation.
11 Set if eciwx or ecowx is used and EAR[E] is cleared.
ISI
00400
An ISI exception is caused when an instruction fetch cannot be performed for any of the
following reasons:
•
The effective (logical) address cannot be translated. That is, there is a page fault for this
portion of the translation, so an ISI exception must be taken to load the PTE (and
possibly the page) into memory.
•
The fetch access is to a direct-store segment.
•
The fetch access violates memory protection. If the key bits (Ks and Kp) in the segment
register and the PP bits in the PTE are set to prohibit read access, instructions cannot be
fetched from this location.
External
interrupt
00500
An external interrupt is caused when MSR[EE] = 1 and the INT signal is asserted.
Alignment
00600
An alignment exception is caused when the 603 cannot perform a memory access for any of
several reasons, such as when the operand of a floating-point load or store operation is in an
I/O segment (SR[T] = 1).
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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