ISLA112P25M datasheet(21/29 Pages) RENESAS

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ISLA112P25M

FN7646 Rev 1.00

Page 21 of 29

November 17, 2011

read from at a given time (again, only in three-wire

mode). If multiple slave devices are selected for reading

at the same time, the results will be indeterminate.

The communication protocol begins with an

instruction/address phase. The first rising SCLK edge

following a high to low transition on CSB determines the

beginning of the two-byte instruction/address command;

SCLK must be static low before the CSB transition. Data

can be presented in MSB-first order or LSB-first order.

The default is MSB-first, but this can be changed by

setting 0x00[6] high. Figures 33 and 34 show the

appropriate bit ordering for the MSB-first and LSB-first

modes, respectively. In MSB-first mode the address is

incremented for multi-byte transfers, while in LSB-first

mode it’s decremented.

In the default mode the MSB is R/W, which determines if

the data is to be read (active high) or written. The next

two bits, W1 and W0, determine the number of data

bytes to be read or written (see Table 6). The lower 13

bits contain the first address for the data transfer. This

relationship is illustrated in Figure 35, and timing values

are given in “Switching Specifications” on page 9.

After the instruction/address bytes have been read, the

appropriate number of data bytes are written to or read

from the ADC (based on the R/W bit status). The data

transfer will continue as long as CSB remains low and

SCLK is active. Stalling of the CSB pin is allowed at any

byte boundary (instruction/address or data) if the

number of bytes being transferred is three or less. For

transfers of four bytes or more, CSB is allowed stall in the

middle of the instruction/address bytes or before the first

data byte. If CSB transitions to a high state after that

point the state machine will reset and terminate the data

transfer.

Figures 37 and 38 illustrate the timing relationships for

2-byte and N-byte transfers, respectively. The operation

for a 3-byte transfer can be inferred from these

diagrams.

SPI Configuration

ADDRESS 0X00: CHIP_PORT_CONFIG

Bit ordering and SPI reset are controlled by this register.

Bit order can be selected as MSB to LSB (MSB first) or

LSB to MSB (LSB first) to accommodate various

microcontrollers.

Bit 7 SDO Active

Bit 6 LSB First

Setting this bit high configures the SPI to interpret serial data

as arriving in LSB to MSB order.

Bit 5 Soft Reset

Setting this bit high resets all SPI registers to default values.

Bit 4 Reserved

This bit should always be set high.

Bits 3:0 These bits should always mirror bits 4:7 to

avoid ambiguity in bit ordering.

ADDRESS 0X02: BURST_END

If a series of sequential registers are to be set, burst

mode can improve throughput by eliminating redundant

addressing. In 3-wire SPI mode the burst is ended by

pulling the CSB pin high. If the device is operated in

2-wire mode the CSB pin is not available. In that case,

setting the burst_end address determines the end of the

transfer. During a write operation, the user must be

cautious to transmit the correct number of bytes based

on the starting and ending addresses.

Bits 7:0 Burst End Address

This register value determines the ending address of the

burst data.

Device Information

ADDRESS 0X08: CHIP_ID

ADDRESS 0X09: CHIP_VERSION

The generic die identifier and a revision number,

respectively, can be read from these two registers.

Indexed Device Configuration/Control

ADDRESS 0X10: DEVICE_INDEX_A

A common SPI map, which can accommodate

single-channel or multi-channel devices, is used for all

Intersil ADC products. Certain configuration commands

(identified as Indexed in the SPI map) can be executed

on a per-converter basis. This register determines which

converter is being addressed for an Indexed command. It

is important to note that only a single converter can be

addressed at a time.

This register defaults to 00h, indicating that no ADC is

addressed. Therefore Bit 0 must be set high in order to

execute any Indexed commands. Error code ‘AD’ is

returned if any indexed register is read from without

properly setting device_index_A.

ADDRESS 0X20: OFFSET_COARSE AND

ADDRESS 0X21: OFFSET_FINE

The input offset of the ADC core can be adjusted in fine

and coarse steps. Both adjustments are made via an

8-bit word as detailed in Table 7.

The default value of each register will be the result of the

self-calibration after initial power-up. If a register is to be

TABLE 6. BYTE TRANSFER SELECTION

[W1:W0]

BYTES TRANSFERRED

4 or more

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