ISLA112P25M

FN7646 Rev 1.00

Page 6 of 29

November 17, 2011

Absolute Maximum Ratings

Thermal Information

AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V

OVDD to OVSS. . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V

AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V

Analog Inputs to AVSS . . . . . . . . . . . -0.4V to AVDD + 0.3V

Clock Inputs to AVSS . . . . . . . . . . . . -0.4V to AVDD + 0.3V

Logic Input to AVSS . . . . . . . . . . . . . -0.4V to OVDD + 0.3V

Logic Inputs to OVSS . . . . . . . . . . . . -0.4V to OVDD + 0.3V

Thermal Resistance (Typical)

JA (°C/W) JC (°C/W)

72 Ld QFN Package (Note 2, 3) . . .

24

0.8

Storage Temperature. . . . . . . . . . . . . . . . -65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . -55°C to +125°C

Maximum Operating Junction Temperature. . . . . . . . +135°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact

product reliability and result in failures not covered by warranty.

NOTES:

2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief

TB379 for details.

3. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,

OVDD = 1.8V, TA = -55°C to +125°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE =Maximum Conversion Rate (per

speed grade).

PARAMETER

SYMBOL

CONDITIONS

MIN

(Note 4)

TYP

MAX

(Note 4) UNITS

DC SPECIFICATIONS (Note 5)

Analog Input

Full-Scale Analog Input Range

VFS

Differential

1.47

VP-P

Input Resistance

RIN

Differential

1000



Input Capacitance

CIN

Differential

1.8

pF

Full Scale Range Temp. Drift

AVTC

Full Temp

90

ppm/°C

Input Offset Voltage

VOS

±2

mV

Gain Error

EG

±0.6

%

Common-Mode Output Voltage

VCM

535

mV

Clock Inputs

Inputs Common Mode Voltage

0.9

V

CLKP, CLKN Input Swing

1.8

V

Power Requirements

1.8V Analog Supply Voltage

AVDD

1.8

V

1.8V Digital Supply Voltage

OVDD

1.8

V

1.8V Analog Supply Current

IAVDD

90

mA

1.8V Digital Supply Current (SDR) (Note 6)

I

OVDD

3mA LVDS

58

mA

1.8V Digital Supply Current (DDR) (Note 6)

I

OVDD

3mA LVDS

39

mA

Power Supply Rejection Ratio

PSRR

30MHz, 200mVP-P signal on AVDD

-36

dB

Total Power Dissipation

Normal Mode (SDR)

PD

3mA LVDS

267

mW

Normal Mode (DDR)

PD

3mA LVDS

234

mW

Nap Mode

PD

84

mW

Sleep Mode

PD

CSB at logic high

2

mW

Nap Mode Wakeup Time (Note 7)

Sample Clock Running

1

µs

Sleep Mode Wakeup Time (Note 7)

Sample Clock Running

1

ms