| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
AND8020D bảng dữ liệu(PDF) 10 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AND8020D bảng dữ liệu(HTML) 10 Page - Analog Devices |
|
10 / 18 page ![]() AND8020/D http://onsemi.com 10 Because the resistor divider network of R1 and R2 is used to generate VTT, the variation in VTT will be intimately tied to the variation in VCC. Differentiating the equation for VTT with respect to VCC yields: DVTT DVCC + R2 (R1 ) R2 ) DVCC (eq. 24) For the nominal case, this equation reduces to: DVTT + 0.6 DVCC (eq. 25) If DVCC = $5% = $0.25 V, then DVTT = $0.15 V. As mentioned previously, the real potential for problems will be if the VOL level can potentially put the output emitter follower out of the active operating region and into cutoff. Because of the relationship between the VCC and VTT levels, the only cutoff risk condition occurs at VCCmin, the lowest value of VCC. Applying the equation for IOLmin under this −5% VCC condition yields: IOLmin + (VOLmin * VTT ) Rt (eq. 26) IOLmin + (4.75 * 1.85) * 2.85 50 + 1.0 mA (eq. 27) The results of this cutoff risk analysis show there is no potential for the output emitter follower to be in cutoff. This would indicate a Thevenin equivalent termination scheme is more robust to variation in VCC. Since the designer has the flexibility of choosing the VTT level via the selection of the R1 and R2 resistors, the following procedure can be used. At −5% minimal variation case for VCC: VCC = 4.75 V VTT = VCC − 2.0 V = 2.75 V R2 = 119 W R1 = 86 W Thus: IOHmax = 23 mA IOLmin = 3.0 mA At +5% minimal variation case for VCC: VCC = 5.25 V VTT = 3.05 V Thus: IOHmax = 28 mA IOLmin = 5.2 mA Although the output currents are slightly higher than nominal, the elimination of emitter follower cutoff risk is well justified. When the equivalent termination resistance matches the line impedance, no reflection occurs because all the energy in the signal is dissipated by the termination. Hence, in comparing properly terminated schemes parallel and Thevenin, a primary consideration is the power supply requirements. As mentioned earlier, the parallel VTT scheme requires an extra power supply; however, the Thevenin termination dissipates 10 times more DC power. Fortunately, this extra power dissipation cannot be seen on the die; therefore, either technique results in similar die junction temperatures. |
|
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |