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AND8020D bảng dữ liệu(PDF) 5 Page - Analog Devices

tên linh kiện AND8020D
Giải thích chi tiết về linh kiện  Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure
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AND8020D bảng dữ liệu(HTML) 5 Page - Analog Devices

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AND8020/D
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5
TERMINATION OF ECL LOGIC DEVICES
SECTION 2. PARALLEL TERMINATION − EXTERNAL AND INTERNAL
Rt
Rt
External
Internal
Near (Standard Pair)
Far (Standard Pair)
Near (Standard Pair)
Far (Standard Pair)
VEE
Rt
VTT
Vt
Rt
Rt
Rt
Rt
Vt1
Vt2
Rt
Rt
Rt
Rt
Vt1
Vt2
VEE
Vto
(Open)
VEE
(Shorted)
VTT
VTT
RE
RE
RE
RE
RE
RE
Parallel termination advantages:
• Method of choice for best circuit performance
• Particularly excellent for driving distributed loads
• Undistorted waveform along the full length of the line
• Decreased power consumption.
Far DC Current Return − VTT
A parallel terminated line is one in which the receiving end
is signal terminated internally or externally (usually to a
voltage VTT) through a resistor (Rt) with a value equal to the
line characteristic impedance (Figure 4). This line also carries
the biasing current for the drivers output far from the driver.
Output current and power dissipation is decreased due to use
of a VTT termination supply. The VTT supply must sustain the
emitter follower output transistor in its active operating region
under all operating conditions. A minimum continuous current
occurs for the most negative VOL, therefore the VTT supply
must remain more negative than the worst case VOLmin and
always sink current.
Standard VTT is 2.0 V below VCC supply. A parallel
resistor, Rt, matching the controlled impedance transmission
line, Z0, connects the signal to the VTT supply. The Parallel
Termination to VTT is shown in Figure 4. The termination
resistors may be internal or external and either ganged into a
Combo pin or offered as Singulated pins. Some devices may
have each internal resistors independently pinned out,
allowing further termination versatility.
Figure 4. Parallel Termination to VTT − Differential and Single−Ended with Combo or Singulated Vt Pins (Far Return)
VTT
Rt = Z0
VTT = VCC −2.0 V
T−Line Z0
VTT
(*or twisted pair)
Driver
Receiver
*T−Line Z0
*T−Line Z0
VTT
R
R
(*or twisted pair)
Driver
Receiver
*T−Line Z0
*T−Line Z0
Vt
Driver
Receiver
External (Far, Diff.)
Internal Termination Combo Pin (Far, Diff.)
VTT
R
R
(*or twisted pair)
Driver
Receiver
*T−Line Z0
*T−Line Z0
Vt1
Internal Termination Singulated Pins (Far, Diff.)
Rt
Rt
Rt
Vt2
External (Far, S.E.)



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