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MPC9893 bảng dữ liệu(PDF) 10 Page - Renesas Technology Corp

tên linh kiện MPC9893
Giải thích chi tiết về linh kiện  3.3V 1:12 LVCMOS PLL Clock Generator
PDF  15 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
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MPC9893 bảng dữ liệu(HTML) 10 Page - Renesas Technology Corp

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MPC9893 REVISION 8 3/16/16
10
©2016 Integrated Device Technology, Inc.
MPC9893 Data Sheet
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
The waveform plots in Figure 9 show the simulation results
of an output driving a single line versus two lines. In both
cases the drive capability of the MPC9893 output buffer is
more than sufficient to drive 50
 transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9893. The output waveform
in Figure 9 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36
 series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL =VS (Z0  (RS+R0 +Z0))
Z0 = 50  || 50 
RS = 36  || 36 
R0 = 14 
VL = 3.0 (25  (18+17+25)
= 1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 10 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
Figure 9. Single versus Dual Waveforms
Figure 10. Optimized Dual Line Termination
Figure 11. CLK0, CLK1 MPC9893 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
Time (ns)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
14
MPC9893
Output
Buffer
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 || 22 = 50 || 50
25
 = 25
Pulse
Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC9893 DUT
VTT
VTT



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