DATASHEET

3.3V 1:12 LVCMOS PLL Clock Generator

MPC9893

MPC9893 REVISION 8 3/16/16

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©2016 Integrated Device Technology, Inc.

The MPC9893 is a 2.5 V and 3.3 V compatible, PLL based intelligent dynamic

clock switch and generator specifically designed for redundant clock distribution

systems. The device receives two LVCMOS clock signals and generates 12

phase aligned output clocks. The MPC9893 is able to detect a failing reference

clock signal and to dynamically switch to a redundant clock signal. The switch

from the failing clock to the redundant clock occurs without interruption of the

output clock signal (output clock slews to alignment). The phase bump typically

caused by a clock failure is eliminated.

The device offers 12 low skew clock outputs organized into two output banks,

each configurable to support the different clock frequencies.

The extended temperature range of the MPC9893 supports

telecommunication and networking requirements. The device employs a fully

differential PLL design to minimize jitter.

Features

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12-output LVCMOS PLL clock generator

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2.5 V and 3.3 V compatible

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IDCS - on-chip intelligent dynamic clock switch

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Automatically detects clock failure

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Smooth output phase transition during clock failover switch

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7.5 – 200 MHz output frequency range

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LVCMOS compatible inputs and outputs

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External feedback enables zero-delay configurations

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Supports networking, telecommunications and computer applications

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Output enable/disable and static test mode (PLL bypass)

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Low skew characteristics: maximum 50 ps output-to-output (within bank)

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48-lead LQFP package, Pb-free

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Ambient operating temperature range of -40 to 85

C

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For functional replacement use 87973

Functional Description

The MPC9893 is a 3.3 V or 2.5 V compatible PLL clock driver and clock generator. The clock generator uses a fully integrated

PLL to generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by one, two,

three, four or eight. The frequency-multiplied clock drives six bank A outputs. Six bank B outputs can run at either the same fre-

quency than bank A or at half of the bank A frequency. Therefore, bank B outputs additionally support the frequency multiplication

of the input reference clock by 3

2 and 12. Bank A and bank B outputs are phase-aligned(1). Due to the external PLL feedback,

the clock signals of both output banks are also phase-aligned(1) to the selected input reference clock, providing virtually zero-de-

lay capability. The integrated IDCS continuously monitors both clock inputs and indicates a clock failure individually for each clock

input. When a false clock signal is detected, the MPC9893 switches to the redundant clock input, forcing the PLL to slowly slew

to alignment and not produce any phase bumps at the outputs. Both clock inputs are interchangeable, also supporting the switch

to a failed clock that was restored. The MPC9893 also provides a manual mode that allows for user-controlled clock switches.

The PLL bypass of the MPC9893 disables the IDCS and PLL-related specifications do not apply. In PLL bypass mode, the

MPC9893 is fully static in order to distribute low-frequency clocks for system test and diagnosis. Outputs of the MPC9893 can

be disabled (high-impedance tristate) to isolate the device from the system. Applying output disable also resets the MPC9893.

On power-up this reset function needs to be applied for correct operation of the circuitry. Please see the application section for

power-on sequence recommendations.

1. At coincident rising edges.

MPC9893

LOW VOLTAGE

2.5 V AND 3.3 V IDCS AND

PLL CLOCK GENERATOR

AE SUFFIX

48-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 932-03

SCALE 2:1

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016